AO4832 30v dual n-channel mosfet general description product summary v ds i d (at v gs =10v) 10a r ds(on) (at v gs =10v) < 13m w r ds(on) (at v gs =4.5v) < 17.5m w 100% uis tested 100% r g tested symbol v ds the AO4832 uses advanced trench technology to provi de excellent r ds(on) with low gate charge. this device is suitable for high side switch in smp s and general purpose applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 30v drain-source voltage 30 g2 d2 s2 g1 d1 s1 g1 s1 g2 s2 d1 d1 d2 d2 2 4 5 1 3 86 7 top view soic-8 top view bottom view pin1 v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jl 90 maximum junction-to-ambient a t a =25c avalanche current c w 2 maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 32 40 74 62.5 -55 to 150 c t a =25c t a =70c c/w r q ja 48 v 20 gate-source voltage 8 55 24 a 22 v drain-source voltage 30 units thermal characteristics parameter typ max mj junction and storage temperature range t a =70c 1.3 power dissipation b p d avalanche energy l=0.1mh c a i d 10 pulsed drain current c continuous drain current g2 d2 s2 g1 d1 s1 g1 s1 g2 s2 d1 d1 d2 d2 2 4 5 1 3 86 7 top view soic-8 top view bottom view pin1 rev 0: jan. 2010 www.aosmd.com page 1 of 6
AO4832 symbol min typ max units bv dss 30 v v ds =30v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.5 1.9 2.5 v i d(on) 55 a 10.8 13 t j =125c 15.5 19 14 17.5 m w g fs 43 s v sd 0.75 1 v i s 2.5 a c iss 610 760 910 pf c oss 88 125 160 pf c rss 40 70 100 pf r g 0.8 1.6 2.4 w q g (10v) 11 14 17 nc q g (4.5v) 5 6.6 8 nc q gs 2.4 nc q gd 3 nc t d(on) 4.4 ns t 9 ns v gs =0v, v ds =15v, f=1mhz switching parameters v ds =0v, v gs =20v zero gate voltage drain current gate-body leakage current drain-source breakdown voltage on state drain current i d =250 m a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =10a reverse transfer capacitance i s =1a,v gs =0v v ds =5v, i d =10a v gs =4.5v, i d =8a diode forward voltage electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions i dss m a v ds =v gs i d =250 m a r ds(on) static drain-source on-resistance m w forward transconductance gate resistance v gs =0v, v ds =0v, f=1mhz total gate charge v gs =10v, v ds =15v, i d =10a gate source charge gate drain charge total gate charge maximum body-diode continuous current input capacitance output capacitance turn-on delaytime dynamic parameters turn-on rise time v =10v, v =15v, r =1.5 w , t r 9 ns t d(off) 17 ns t f 6 ns t rr 5.6 7 8 ns q rr 6.4 8 9.6 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. i f =10a, di/dt=500a/ m s body diode reverse recovery time turn-off fall time body diode reverse recovery charge i f =10a, di/dt=500a/ m s turn-on rise time turn-off delaytime v gs =10v, v ds =15v, r l =1.5 w , r gen =3 w a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. the value in any given application depends on the user' s specific board design. b. the power dissipation p d is based on t j(max) =150 c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150 c. ratings are based on low frequency and duty cycl es to keep initialt j =25 c. d. the r q ja is the sum of the thermal impedence from junction t o lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedence which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150 c. the soa curve provides a single pulse rating. rev 0: jan. 2010 www.aosmd.com page 2 of 6
AO4832 typical electrical and thermal characteristics 17 52 10 0 18 0 5 10 15 20 25 30 0 1 2 3 4 5 i d (a) v gs (volts) figure 2: transfer characteristics (note e) 5 10 15 20 0 5 10 15 20 25 30 r ds(on) (m w ww w ) i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 normalized on-resistance temperature (c) figure 4: on-resistance vs. junction temperature (note e) v gs =4.5v i d =8a v gs =10v i d =10a 25 c 125 c v ds =5v v gs =4.5v v gs =10v 0 20 40 60 80 100 0 1 2 3 4 5 i d (a) v ds (volts) fig 1: on-region characteristics (note e) v gs =3v 3.5v 6v 7v 10v 4.5v 5v 4v 40 0 5 10 15 20 25 30 0 1 2 3 4 5 i d (a) v gs (volts) figure 2: transfer characteristics (note e) 5 10 15 20 0 5 10 15 20 25 30 r ds(on) (m w ww w ) i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s (a) v sd (volts) figure 6: body-diode characteristics (note e) 25 c 125 c 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 normalized on-resistance temperature (c) figure 4: on-resistance vs. junction temperature (note e) v gs =4.5v i d =8a v gs =10v i d =10a 5 10 15 20 25 30 2 4 6 8 10 r ds(on) (m w ww w ) v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) 25 c 125 c v ds =5v v gs =4.5v v gs =10v i d =10a 25 c 125 c 0 20 40 60 80 100 0 1 2 3 4 5 i d (a) v ds (volts) fig 1: on-region characteristics (note e) v gs =3v 3.5v 6v 7v 10v 4.5v 5v 4v rev 0: jan. 2010 www.aosmd.com page 3 of 6
AO4832 typical electrical and thermal characteristics 0 2 4 6 8 10 0 3 6 9 12 15 v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 capacitance (pf) v ds (volts) figure 8: capacitance characteristics c iss c oss c rss v ds =15v i d =10a 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 i d (amps) v ds (volts) figure 10: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150 c t a =25 c 100 m s 10ms 1 10 100 1 10 100 1000 i ar (a) peak avalanche current time in avalanche, t a ( m mm m s) figure 9: single pulse avalanche capability (note c ) t a =25 c t a =150 c t a =100 c t a =125 c 0 2 4 6 8 10 0 3 6 9 12 15 v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 capacitance (pf) v ds (volts) figure 8: capacitance characteristics c iss c oss c rss v ds =15v i d =10a 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 power (w) pulse width (s) figure 11: single pulse power rating junction-to-am bient (note f) t a =25 c 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 i d (amps) v ds (volts) figure 10: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150 c t a =25 c 100 m s 10ms 1 10 100 1 10 100 1000 i ar (a) peak avalanche current time in avalanche, t a ( m mm m s) figure 9: single pulse avalanche capability (note c ) t a =25 c t a =150 c t a =100 c t a =125 c rev 0: jan. 2010 www.aosmd.com page 4 of 6
AO4832 typical electrical and thermal characteristics 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 z q qq q ja normalized transient thermal resistance pulse width (s) figure 12: normalized maximum transient thermal imp edance (note f) single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse r q ja =90 c/w 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 z q qq q ja normalized transient thermal resistance pulse width (s) figure 12: normalized maximum transient thermal imp edance (note f) single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse r q ja =90 c/w rev 0: jan. 2010 www.aosmd.com page 5 of 6
AO4832 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off id + l vgs vds bv unclamped inductive switching (uis) test circuit & waveforms vds dss 2 e = 1/2 li ar ar - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev 0: jan. 2010 www.aosmd.com page 6 of 6
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